PIC16F688-ESLASHST datasheet(33/174 Pages) MICROCHIP

33 / 174 page

 2004 Microchip Technology Inc.

Preliminary

DS41203B-page 31

PIC16F688

4.0

I/O PORTS

There are as many as twelve general purpose I/O pins

available.

Depending

which

peripherals

are

enabled, some or all of the pins may not be available as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

4.1

PORTA and the TRISA Registers

PORTA is a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA. Setting

a TRISA bit (= 1) will make the corresponding PORTA

pin an input (i.e., put the corresponding output driver in

a Hi-impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

The exception is RA3, which is input only and its TRISA

bit will always read as ‘1’. Example 4-1 shows how to

initialize PORTA.

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modified and then written to the port

data latch. RA3 reads ‘0’ when MCLRE = 1.

The TRISA register controls the direction of the

PORTA pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISA

inputs. I/O pins configured as analog input always read

‘0’.

EXAMPLE 4-1:

INITIALIZING PORTA

4.2

Additional Pin Functions

Every PORTA pin on the PIC16F688 has an interrupt-

on-change option and a weak pull-up option. PORTA

also provides an Ultra Low-Power Wake-up option. The

next three sections describe these functions.

4.2.1

WEAK PULL-UPS

Each of the PORTA pins, except RA3, has an individu-

ally configurable internal weak pull-up. Control bits

WPUAx enable or disable each pull-up. Refer to

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset by the

RAPU bit (Option<7>). A weak pull-up is automatically

enabled for RA3 when configured as MCLR and

_disabled when RA3 is an I/O. There is no software

control of the MCLR pull-up.

PORTA – PORTA REGISTER (ADDRESS: 05h OR 105h)

Note:

Additional information on I/O ports may be

found in the “PICmicro® Mid-Range MCU

Family Reference Manual” (DS33023).

Note:

The ANSEL (91h) and CMCON0 (19h)

registers must be initialized to configure

an analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

BCF

STATUS,RP0

;Bank 0

CLRF

PORTA

;Init PORTA

MOVLW

07h

;Set RA<2:0> to

MOVWF

CMCON0

;digital I/O

BSF

STATUS,RP0

;Bank 1

CLRF

ANSEL

;digital I/O

MOVLW

0Ch

;Set RA<3:2> as inputs

MOVWF

TRISA

;and set RA<5:4,1:0>

;as outputs

BCF

STATUS,RP0

;Bank 0

U-0

R/W-x

R/W-0

—

RA5

RA4

RA3

RA2

RA1

RA0

bit 7

bit 0

bit 7-6:

Unimplemented: Read as ‘0’

bit 5-0:

PORTA<5:0>: PORTA I/O pins

= Port pin is > VIH

= Port pin is < VIL

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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