TDA9321 datasheet(30/44 Pages) PHILIPS

30 / 44 page

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

∆V(clamp)(n)

clamping offset between

pins UO and VO

−−

input impedance

−−

Ω

VERTICAL OSCILLATOR; note 34

ffr

free-running frequency

50 Hz mode

−

60 Hz mode

−

flock

frequency locking range

−

64.5

D/D

divider ratio

not locked

−

625/525

−

lines

locking range

488

−

722

lines/

frame

VERTICAL PULSE OUTPUT (PIN VA)

VOH

HIGH-level output voltage

Io(source) = 2 mA

4.0

5.0

5.5

VOL

LOW-level output voltage

Io(sink) =2mA

−

0.2

0.4

Io(sink)

output sink current

−−

Io(source)

output source current

−−

pulse width

fVA =50Hz

−

2.5

−

lines

fVA =60Hz

−

3.0

−

lines

delay between start of vertical

sync of input and positive edge

of vertical pulse on pin VA

note 35

−

37.7

−µs

output impedance

bit ECL = 1

−−

Ω

SANDCASTLE OUTPUT (PIN SCO)

General

zero level voltage

0.5

1.0

Io(sink)

output sink current

−

0.5

−

Horizontal/vertical blanking

output voltage level

2.2

2.5

2.8

Io(source)

output source current

−

0.7

−

tW(h)

horizontal blanking pulse width

−

−µs

delay between start horizontal

blanking and start clamping

pulse

−

6.4

−µs

Clamping pulse

output voltage level

4.2

4.5

4.8

Io(source)

output source current

−

0.7

−

pulse width

−

3.6

−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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