DSPIC33FJ12MC02ESS datasheet(155/284 Pages) MICROCHIP

155 / 284 page

Preliminary

DS70265B-page 153

dsPIC33FJ12MC201/202

14.16 PWM Special Event Trigger

The PWM module has a Special Event Trigger that

allows ADC conversions to be synchronized to the

PWM time base. The ADC sampling and conversion

time can be programmed to occur at any point within

the PWM period. The Special Event Trigger allows the

programmer to minimize the delay between the time

when ADC conversion results are acquired and the

time when the duty cycle value is updated.

The PWM Special Event Trigger has an SFR named

PxSECMP, and five control bits to control its operation.

The PxTMR value for which a Special Event Trigger

should occur is loaded into the PxSECMP register.

When the PWM time base is in Up/Down Count mode,

an additional control bit is required to specify the

counting phase for the Special Event Trigger. The

count phase is selected using the SEVTDIR control bit

in the PxSECMP SFR:

• If the SEVTDIR bit is cleared, the Special Event

Trigger occurs on the upward counting cycle of

the PWM time base.

• If the SEVTDIR bit is set, the Special Event Trig-

ger occurs on the downward count cycle of the

PWM time base.

The SEVTDIR control bit has no effect unless the PWM

time base is configured for an Up/Down Count mode.

14.16.1

SPECIAL EVENT TRIGGER

POSTSCALER

The PWM Special Event Trigger has a postscaler that

allows a 1:1 to 1:16 postscale ratio. The postscaler is

configured by writing the SEVOPS<3:0> control bits in

the PWMxCON2 SFR.

The special event output postscaler is cleared on the

following events:

• Any write to the PxSECMP register

• Any device Reset

14.17 PWM Operation During CPU Sleep

Mode

The Fault A and Fault B input pins can wake the CPU

from Sleep mode. The PWM module generates an

interrupt if either of the Fault pins is driven low while in

Sleep mode.

14.18 PWM Operation During CPU Idle

Mode

The PxTCON SFR contains a PTSIDL control bit. This

bit determines if the PWM module will continue to

operate or stop when the device enters Idle mode. If

PTSIDL = 0, the module will continue to operate. If

PTSIDL = 1, the module will stop operation as long as

the CPU remains in Idle mode.

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