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DSPIC33FJ12MC02ESS bảng dữ liệu(PDF) 60 Page - Microchip Technology |
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DSPIC33FJ12MC02ESS bảng dữ liệu(HTML) 60 Page - Microchip Technology |
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60 / 284 page  dsPIC33FJ12MC201/202 DS70265B-page 58 Preliminary © 2007 Microchip Technology Inc. 5.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 7.0 “Oscillator Configuration” for further details. TABLE 5-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. The system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code also depends on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the Phase-Locked Loop (PLL) lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source Determinant POR Oscillator Configuration bits (FNOSC<2:0>) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR Reset Type Clock Source SYSRST Delay System Clock Delay FSCM Delay Notes POR EC, FRC, LPRC TPOR + TSTARTUP + TRST —— 1, 2, 3 ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6 BOR EC, FRC, LPRC TSTARTUP + TRST —— 3 ECPLL, FRCPLL TSTARTUP + TRST TLOCK TFSCM 3, 5, 6 XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 3, 4, 6 XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 3, 4, 5, 6 MCLR Any Clock TRST —— 3 WDT Any Clock TRST —— 3 Software Any Clock TRST —— 3 Illegal Opcode Any Clock TRST —— 3 Uninitialized W Any Clock TRST —— 3 Trap Conflict Any Clock TRST —— 3 Note 1: TPOR = Power-on Reset delay (10 μs nominal). 2: TSTARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down states, including waking from Sleep mode, only if the regulator is enabled. 3: TRST = Internal state Reset time (20 μs nominal). 4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: TLOCK = PLL lock time (20 μs nominal). 6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal). |
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