DSPIC33FJ12MC02ESS datasheet(148/284 Pages) MICROCHIP

148 / 284 page

dsPIC33FJ12MC201/202

DS70265B-page 146

Preliminary

14.3

PWM Time Base

The PWM time base is provided by a 15-bit timer with

a prescaler and postscaler. The time base is accessible

via the PXTMR SFR. PXTMR<15> is a read-only status

bit, PTDIR, that indicates the present count direction of

the PWM time base.

• If PTDIR is cleared, PXTMR is counting upward.

• If PTDIR is set, PxTMR is counting downward.

The PWM time base is configured using the PxTCON

SFR. The time base is enabled or disabled by setting

or clearing the PTEN bit in the PXTCON SFR. PXTMR

is not cleared when the PTEN bit is cleared in software.

The PXTPER SFR sets the counting period for

PXTMR. The user application must write a 15-bit value

to PXTPER<14:0>. When the value in PXTMR<14:0>

matches the value in PXTPER<14:0>, the time base

will either reset to ‘0’ or reverse the count direction on

the next occurring clock cycle. The action taken

depends on the operating mode of the time base.

The PWM time base can be configured for four different

modes of operation:

• Free-Running mode

• Single-Shot mode

• Continuous Up/Down Count mode

• Continuous Up/Down Count mode with interrupts

for double updates

These four modes are selected by the PTMOD<1:0>

bits in the PXTCON SFR. The Up/Down Count modes

support center-aligned PWM generation. The Single-

Shot mode allows the PWM module to support pulse

control of certain Electronically Commutative Motors

(ECMs).

The interrupt signals generated by the PWM time base

depend on the mode selection bits (PTMOD<1:0>) and

the postscaler bits (PTOPS<3:0>) in the PXTCON SFR.

14.3.1

FREE-RUNNING MODE

In Free-Running mode, the PWM time base counts

upwards until the value in the PWM Time Base Period

reset on the following input clock edge, and the time

base will continue to count upward as long as the PTEN

bit remains set.

When the PWM time base is in the Free-Running mode

(PTMOD<1:0> = 00), an interrupt event is generated

each time a match with the PXTPER register occurs

and the PXTMR register is reset to zero. The postscaler

selection bits can be used in this mode of the timer to

reduce the frequency of interrupt events.

14.3.2

SINGLE-SHOT MODE

In Single-Shot mode, the PWM time base begins

counting upward when the PTEN bit is set. When the

value in the PXTMR register matches the PXTPER reg-

ister, the PXTMR register will be reset on the following

input clock edge, and the PTEN bit will be cleared by

the hardware to halt the time base.

When the PWM time base is in Single-Shot mode

(PTMOD<1:0> = 01), an interrupt event is generated

when a match with the PXTPER register occurs. The

PxTMR register is reset to zero on the following input

clock edge and the PTEN bit is cleared. The postscaler

selection bits have no effect in this mode of the timer.

14.3.3

CONTINUOUS UP/DOWN COUNT

MODES

In Continuous Up/Down Count modes, the PWM time

base counts upward until the value in the PXTPER

downwards on the following input clock edge. The

PTDIR bit in the PXTMR SFR is read-only and

indicates the counting direction. The PTDIR bit is set

when the timer counts downward.

In the Up/Down Count mode (PTMOD<1:0> = 10), an

interrupt event is generated each time the value of the

PXTMR register becomes zero and the PWM time base

begins to count upward. The postscaler selection bits

can be used in this mode of the timer to reduce the

frequency of interrupt events.

Note:

If the PWM Period register is set to

0x0000, the timer will stop counting and

the interrupt and Special Event Trigger will

not be generated, even if the special event

value is also 0x0000. The module will not

update the PWM Period register if it is

already at 0x0000; therefore, the user

application must disable the module in to

update the PWM Period register.

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