MCP3301

DS21700C-page 4

© 2007 Microchip Technology Inc.

Reference Input

Voltage Range

0.4

—

V

DD

V

Note 2

Current Drain

—

—

100

0.001

150

3

µA

µA

CS = V

Analog Inputs

Full-Scale Input Span

IN(+)-IN(-)

-V

REF

—V

REF

V

Absolute Input Voltage

IN(+)

-0.3

—

V

IN(-)

-0.3

—

V

Leakage Current

—

0.001

±1

µA

Switch Resistance

R

S

—1

—

k

Ω

See Figure 6-3

Sample Capacitor

C

SAMPLE

—

25

—

pF

See Figure 6-3

Digital Input/Output

Data Coding Format

Binary Two’s Complement

High Level Input Voltage

V

IH

0.7 V

DD

——

V

Low Level Input Voltage

V

IL

—

—

0.3 V

DD

V

High Level Output Voltage

V

OH

4.1

—

—

V

I

Low Level Output Voltage

V

OL

——

0.4

V

I

Input Leakage Current

I

LI

-10

—

10

µA

V

Output Leakage Current

I

LO

-10

—

10

µA

V

Pin Capacitance

C

—

—

10

pF

T

Timing Specifications

Clock Frequency (Note 8)

f

CLK

0.085

0.085

—

—

1.7

0.85

MHz

MHz

V

V

Clock High Time

t

HI

275

—

—

ns

Note 5

Clock Low Time

t

LO

275

—

—

ns

Note 5

CS Fall To First Rising CLK Edge

t

SUCS

100

—

—

ns

CLK Fall To Output Data Valid

t

DO

—

—

125

200

ns

ns

V

V

CLK Fall To Output Enable

t

EN

—

—

125

200

ns

ns

V

V

CS Rise To Output Disable

t

DIS

—

—

100

ns

See test circuits, Figure 3-1

(Note 1)

CS Disable Time

t

CSH

580

—

—

ns

D

—

—

100

ns

See test circuits, Figure 3-1; Note 1

D

—

—

100

ns

See test circuits, Figure 3-1; Note 1

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V

configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with

T

Parameter

Symbol

Min

Typ

Max

Units

Conditions

Note

1:

This specification is established by characterization and not 100% tested.

2: See characterization graphs that relate converter performance to V

5: Maximum clock frequency specification must be met.

6: V

7: MSOP devices are only specified at 25°C and +85°C.

8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.