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MCP3301-CI/MS bảng dữ liệu(PDF) 21 Page - Microchip Technology |
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MCP3301-CI/MS bảng dữ liệu(HTML) 21 Page - Microchip Technology |
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21 / 32 page ![]() © 2007 Microchip Technology Inc. DS21700C-page 21 MCP3301 7.2 Communicating with the MCP3301 Communication with the device is completed using a standard SPI compatible serial interface. Initiating com- munication with the MCP3301 begins with the CS going low. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The device will begin to sample the analog input on the first rising edge of CLK after CS goes low. The sample period will end in the falling edge of the second clock, at which time the device will output a low null bit. The next 13 clocks will output the result of the conversion with the sign bit first, followed by the 12 remaining data bits, as shown in Figure 7-2. Data is always output from the device on the falling edge of the clock. If all 13 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 7-3. If more clocks are pro- vided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. FIGURE 7-2: Communication with MCP3301 (MSB first Format). FIGURE 7-3: Communication with MCP3301 (LSB first Format). CS CLK D OUT tSAMPLE Power Down t SUCS tACQ t CONV t DATA** * After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data, followed by zeros indefinitely. See Figure 7-2 below. ** t DATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. t CSH NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* HI-Z HI-Z NULL BIT SB B11 B10 B9 SB CS CLK D OUT tSAMPLE Power Down t SUCS tACQ t CONV t DATA** * After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefi- nitely. ** t DATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. t CSH NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 HI-Z B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 SB * HI-Z SB B11 |
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