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TMP112DX bảng dữ liệu(PDF) 20 Page - Texas Instruments |
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TMP112DX bảng dữ liệu(HTML) 20 Page - Texas Instruments |
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20 / 46 page ![]() 1 Start By Host ACK By TMP112 ACK By TMP112 Start By Host ACK By TMP112 ACK By Host From TMP112 1 9 1 9 1 9 1 9 SDA SCL 0 0 1 R /W 0 0 0 0 0 0 P1 P0 … … … … SDA (Continued) SCL (Continued) SDA (Continued) SCL (Continued) R/W D7 D6 D5 D4 D3 D2 D1 D0 Stop By Host ACK By Host From TMP112 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Frame 1 Two-Wire Device Address Byte Frame 2 Pointer Register Byte Frame 4 Data Byte 1 Read Register Frame 3 Two-Wire Device Address Byte Frame 5 Data Byte 2 Read Register 1 0 0 1 0 0 A1 (1) A0 (1) Stop By Host A1 (1) A0 (1) (2) (3) NOTE: (1) The value of A0 and A1 are determined by the ADD0 pin. (2) Host should leave SDA high to terminate a single-byte read operation. (3) Host should leave SDA high to terminate a two-byte read operation. Figure 7-5. Two-Wire Timing Diagram for Read Word Format Start By Host ACK By TMP112 From TMP112 NACK By Host Stop By Host 1 9 1 9 SDA SCL ALERT 0 0 0 1 1 0 0 R/W 1 0 0 1 Status Frame 2 Device Address Byte Frame 1 SMBus ALERT Response Address Byte A1 A0 (1) (1) NOTE: (1) The value of A0 and A1 are determined by the ADD0 pin. Figure 7-6. Timing Diagram for SMBus ALERT TMP112, TMP112D SBOS473L – MARCH 2009 – REVISED JULY 2024 www.ti.com 20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TMP112 TMP112D |
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