TMP112DX datasheet(17/46 Pages) TI1

17 / 46 page

the R/W bit low. Every write operation to the TMP112 family requires a value for the pointer register (see Figure

7-4).

When reading from the TMP112 family, the last value stored in the pointer register by a write operation is used

to determine which register is read by a read operation. To change the register pointer for a read operation, a

new value must be written to the pointer register. This action is accomplished by issuing a target-address byte

with the R/W bit low, followed by the pointer register byte. No additional data are required. The controller can

then generate a START condition and send the target address byte with the R/W bit high to initiate the read

command. See Figure 7-5 for details of this sequence. If repeated reads from the same register are desired,

continuously sending the pointer register bytes is not necessary because the TMP112 family retains the pointer

7.3.2.4 Target Mode Operations

The TMP112 family can operate as a target receiver or target transmitter. As a target device, the TMP112 family

never drives the SCL line.

7.3.2.4.1 Target Receiver Mode

The first byte transmitted by the controller is the target address with the R/W bit low. The TMP112 family then

acknowledges reception of a valid address. The next byte transmitted by the controller is the pointer register.

The TMP112 family then acknowledges reception of the pointer register byte. The next byte or bytes are written

to the register addressed by the pointer register. The TMP112 family acknowledges reception of each data byte.

The controller can terminate data transfer by generating a START or STOP condition.

7.3.2.4.2 Target Transmitter Mode

The first byte transmitted by the controller is the target address with the R/W bit high. The target acknowledges

reception of a valid target address. The next byte is transmitted by the target and is the most significant byte of

the register indicated by the pointer register. The controller acknowledges reception of the data byte. The next

byte transmitted by the target is the least significant byte. The controller acknowledges reception of the data

byte. The controller can terminate data transfer by generating a not-acknowledge on reception of any data byte

or by generating a START or STOP condition.

7.3.2.5 SMBus Alert Function

The TMP112 family supports the SMBus alert function. When the TMP112 family operates in interrupt mode (TM

= 1), the ALERT pin can be connected as an SMBus alert signal (when the ALERT pin is available). Irrespective

of the availability of the ALERT pin, the alert status is set. When a controller senses that an alert condition is

present on the alert line, the controller sends an SMBus ALERT command (0001 1001) to the bus. If the ALERT

pin is active or the alert is set, the device acknowledges the SMBus ALERT command and responds by returning

the target address on the SDA line. The eighth bit (LSB) of the target address byte indicates if the alert condition

is caused by the temperature exceeding T(HIGH) or falling below T(LOW). The LSB is high if the temperature is

greater than T(HIGH), or low if the temperature is less than T(LOW). Refer to the Figure 7-6 section for details of

this sequence.

If multiple devices on the bus respond to the SMBus ALERT command, arbitration during the target address

portion of the SMBus ALERT command determines which device clears the alert status of that device. The

device with the lowest two-wire address wins the arbitration. If the TMP112 family wins the arbitration, the

TMP112 family ALERT pin becomes inactive and/or clears the status bit at the completion of the SMBus ALERT

command. If the TMP112 family loses the arbitration, the TMP112 family ALERT pin and/or the status bit remains

active.

7.3.2.6 General Call

The TMP112 family responds to a two-wire general-call address (0000 000) if the eighth bit is 0. The device

acknowledges the general-call address and responds to commands in the second byte. If the second byte is

0000 0110, the TMP112 family internal registers are reset to power-up values. The TMP112 family does not

support the general-address acquire command.

www.ti.com

TMP112, TMP112D

SBOS473L – MARCH 2009 – REVISED JULY 2024

Submit Document Feedback

Product Folder Links: TMP112 TMP112D

TMP112DX bảng dữ liệu(PDF) 17 Page - Texas Instruments

TMP112DX bảng dữ liệu(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL