24LC41A-SLASHP datasheet(3/18 Pages) MICROCHIP

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 2003 Microchip Technology Inc.

DS21176D-page 3

24LC41A

TABLE 1-2:

AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)

DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port

Parameter

Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency (DSCL and

MSCL)

FCLK

—100

—

400

kHz

Clock high time (DSCL and

MSCL)

THIGH

4000

—

600

—

Clock low time (DSCL and

MSCL)

TLOW

4700

—

1300

—

DSCL, DSDA, MSCL &

MSDA rise time

—1000

—

300

(Note 1)

DSCL, DSDA, MSCL &

MSDA fall time

—

300

—

300

(Note 1)

Start condition hold time

THD:STA

4000

—

600

—

After this period the first clock

pulse is generated

Start condition setup time

TSU:STA

4700

—

600

—

Only relevant for repeated

Start condition

Data input hold time

THD:DAT

0—

—

(Note 2)

Data input setup time

TSU:DAT

250

—

100

—

Stop condition setup time

TSU:STO

4000

—

600

—

Output valid from clock

TAA

—3500

—

900

(Note 2)

Bus free time

TBUF

4700

—

1300

—

Time the bus must be free

before a new transmission

can start

Output fall time from VIH

min to VIL max

TOF

—

250

20 + .1

250

(Note 1), CB

≤ 100 pF

Input filter spike suppres-

sion (DSCL, DSDA, MSCL

& MSDA pins)

TSP

—

(Note 3)

Write cycle time

TWR

—

Byte or Page mode

Endurance

—

cycles

25°C, Vcc = 5.0V, Block mode

(Note 4)

DDC Monitor Port Transmit-only mode Parameters

Output valid from VCLK

TVAA

—

2000

—

1000

VCLK high time

TVHIGH

4000

—

600

—

VCLK low time

TVLOW

4700

—

1300

—

VCLK setup time

TVHST

0—

—

VCLK hold time

TSPVL

4000

—

600

—

Mode transition time

TVHZ

—

500

—

500

Transmit-only power-up

time

TVPU

0—

—

Input filter spike

suppression (VCLK pin)

TSPV

—

100

—

100

Note 1:

Not 100% tested. CB = total capacitance of one bus line in pF.

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop

conditions.

The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a TI specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.

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