82546EB datasheet(13/47 Pages) INTEL

13 / 47 page

Networking Silicon — 82546EB

Datasheet

2.7

Technology Features

Supports little endian byte ordering for both 32 and 64

bit systems and big endian byte ordering for 64 bit

systems

•

Portable across application architectures

Provides loopback capabilities

•

Validates silicon integrity

Single-pin LAN disable function

•

Allows LAN port enabling and disabling through

BIOS control (OS not required) for both ports

Features

Benefits

364-pin Ball Grid Array (BGA) package

•

21 mm x 21 mm component makes LOM designs

easier

Footprint compatible with the 82544GC, 82545EM,

and 82545GM single port gigabit Ethernet controllers

•

Single port or dual port implementation on the

same board with minor option changes.

Implemented in 0.15u CMOS process

•

Offers lowest geometry to minimize power and

size while maintaining Intel quality reliability

standards

0 C to 55 C (maximum) operating temperature

Heat sink or forced airflow not required

65 C to 140 C storage temperature range

•

Simple thermal design

3.3 V PCI signaling with an average power dissipation

of 3.5 W

•

Lower power requirements

Features

Benefits

82546EB bảng dữ liệu(PDF) 13 Page - Intel Corporation

82546EB bảng dữ liệu(HTML) 13 Page - Intel Corporation

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