LTC6906 datasheet(20/30 Pages) AD

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LTC6990

Rev. D

For more information www.analog.com

APPLICATIONS INFORMATION

Modulation Bandwidth and Settling Time

The LTC6990 will respond to changes in ISET up to a –3dB

bandwidth of 0.4 • fOUT (see Figure 15). This makes it easy

to stabilize a feedback loop around the LTC6990, since it

does not introduce a low-frequency pole.

Settling time depends on the master oscillator frequency.

Following a 2x or 0.5x step change in ISET, the output

frequency takes approximately six master clock cycles

(6 • tMASTER) to settle to within 1% of the final value. An

example is shown in Figure 16.

Power Supply Current

The power supply current varies with frequency, supply

voltage and output loading. It can be estimated under any

condition using the following equation:

IS(TYP) ≈ V+• fMASTER •7pF+ V+• fOUT•(13pF+CLOAD)

V+

480k

V+

2•RLOAD

+1.75•ISET +50µA

The equation is also valid for OE = 0 (output disabled),

with fOUT = 0Hz.

Figure 15. Modulation Frequency Response

Figure 16. Settling Time

fMOD/fOUT (Hz/Hz)

0.1

–20

–30

–10

–40

6990 F15

VCTRL = 0.536V + 0.278V

• SIN(2π•fMOD•t)

fOUT =18.75kHz ±10%

–3dB AT 0.4•fOUT

RSET = 200k

RVCO = 464k

DIVCODE = 4(÷16)

10µs/DIV

6990 F16

VCTRL

2V/DIV

fOUT

50kHz/DIV

OUT

2V/DIV

V+ = 3.3V, DIVCODE = 0

RSET = 200k, RVCO = 464k

fOUT = 175kHz AND 350kHz

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