LLCC68 datasheet(98/106 Pages) SEMTECH

98 / 106 page

LLCC68

Data Sheet

Rev. 1.0

DS.LLCC68.W.APP

July 2019

98 of 106

Semtech

www.semtech.com

Note: using the described workaround will improve the chip functionality, but is not required to ensure long-term reliability,

which is guaranteed with or without workaround.

15.2.2 Workaround

During chip initialization, the register TxClampConfig should be modified to optimize the PA clamping threshold. Bits 4-1

must be set to “1111” (default value “0100”).

This register modification must be done after a Power On Reset, or a wake-up from cold Start.

The following pseudo-code can be used as a reference to implement the fix:

15.3 Implicit Header Mode Timeout Behavior

15.3.1 Description

When receiving LoRa® packets in Rx mode with Timeout active, and no header (Implicit Mode), the timer responsible for

generating the Timeout (based on the RTC timer) is not stopped on RxDone event. Therefore, it may trigger an unexpected

timeout in any subsequent mode where the RTC isn’t re-invoked, and therefore reset and re-programmed.

15.3.2 Workaround

It is advised to add the following commands after ANY Rx with Timeout active sequence, which stop the RTC and clear the

timeout event, if any. The register at address 0x0902 will be used to stop the counter, while the register at address 0x0944

will clear the potential event.

The following pseudo-code can be used as a reference to implement the fix:

15.4 Optimizing the Inverted IQ Operation

15.4.1 Description

When exchanging LoRa® packets with inverted IQ polarity, some packet losses may be observed for longer packets.

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