LLCC68 datasheet(97/106 Pages) SEMTECH

97 / 106 page

LLCC68

Data Sheet

Rev. 1.0

DS.LLCC68.W.APP

July 2019

97 of 106

Semtech

www.semtech.com

15. Known Limitations

This section summarizes the known limitations of the LLCC68 chip, and the related workarounds.

15.1 Modulation Quality with 500 kHz LoRa® Bandwidth

15.1.1 Description

Some sensitivity degradation may be observed on any LoRa device, when receiving signals transmitted by the LLCC68 with

a LoRa BW of 500 kHz.

15.1.2 Workaround

Before any packet transmission, bit #2 at address 0x0889 shall be set to:

•

0 if the LoRa BW = 500 kHz

•

1 for any other LoRa BW

•

1 for any (G)FSK configuration

The following pseudo-code can be used before each packet transmission, to properly configure the chip:

15.2 Better Resistance of the LLCC68 Tx to Antenna Mismatch

15.2.1 Description

The LLCC68 platform embeds a Power Amplifier (PA) clamping mechanism, backing-off the power when over-voltage

conditions are detected internally. This method is put in place to protect the internal devices and ensure long-term

reliability of the chip. Considering a high-power operation of the LLCC68 (supporting +22dBm on-chip), these “clamping”

devices are overly protective, causing the chip to back-down its output power when even a reasonable mismatch is

detected at the PA output. The observation is typically 5 to 6 dB less output power than the expected.

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