TDA4887 datasheet(34/68 Pages) PHILIPS

34 / 68 page

2001 Oct 19

Philips Semiconductors

Product speciﬁcation

160 MHz bus-controlled monitor video

preampliﬁer

TDA4887PS

Table 4

Subaddress and data byte format

Notes

1. See Table 3 (Subaddress byte format).

2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0).

3. Under certain conditions the nominal values lead to nominal colour signals, etc. (see notes 1 and 3 of

Chapter “Characteristics” and Figs 4 to 6).

After power-up and after internal Power-on reset of the I2C-bus the registers are set to the following values:

a) Control bit FPOL to logic 1.

b) Control bits DISV, DISO and BRI to logic 0.

c) All other alignment registers to logic 0 (minimum value for control registers).

4. Data bit.

5. X means don’t care but the bits are preferably set to logic 0 for software compatibility with other video ICs that have

the same slave address.

FUNCTION

SUBADDRESS(1)

DATA BYTE(2)

NOMINAL

VALUE(3)

DIRECT

MODE

BUFFERED

MODE

D7(4) D6(4)

D5(4)

D4(4)

D3(4)

D2(4)

D1(4)

D0(4)

Control register

00H

80H

X(5)

BRI

X(5)

FPOL DISV DISO

X(5)

08H

Brightness control

01H

81H

A17

A16

A15

A14

A13

A12

A11

A10

40H

Contrast control

02H

82H

A27

A26

A25

A24

A23

A22

A21

A20

FFH

OSD contrast

control

03H

83H

X(5)

A33

A32

A31

A30

0FH

Gain control

channel 1

04H

84H

A47

A46

A45

A44

A43

A42

A41

A40

FFH

Gain control

channel 2

05H

85H

A57

A56

A55

A54

A53

A52

A51

A50

FFH

Gain control

channel 3

06H

86H

A67

A66

A65

A64

A63

A62

A61

A60

FFH

Black level

reference channel 1

07H

87H

A77

A76

A75

A74

A73

A72

A71

A70

−

Black level

reference channel 2

08H

88H

A87

A86

A85

A84

A83

A82

A81

A80

−

Black level

reference channel 3

09H

89H

A97

A96

A95

A94

A93

A92

A91

A90

−

Black level for

AC coupling

0AH

8AH

X(5)

AA2

AA1

AA0

−

Depth of pedestal

blanking

0BH

8BH

X(5)

AB1

AB0

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