TDA4887PS datasheet(14/68 Pages) PHILIPS

14 / 68 page

2001 Oct 19

Philips Semiconductors

Product speciﬁcation

160 MHz bus-controlled monitor video

preampliﬁer

TDA4887PS

tdead(I2C)

I2C-bus receiver dead time

after synchronizing vertical

blanking pulse following a

completed I2C-bus buffered

mode transmission

leading edge threshold

VCLI = 1.4 V; note 7

−−

µs

tdl5

delay between leading

edges of vertical blanking

input pulse and signal

blanking at signal outputs

VHFB < 0.8 V; input pulse

rising and falling edges

= 50 ns/V; threshold for

vertical blanking with rising

edge VCLI = 1.4 V; threshold

for vertical blanking with

falling edge VCLI =3V;

see Fig.7

−

270

−

tdt5

delay between trailing edges

of vertical blanking input

pulse and signal blanking at

signal outputs

VHFB < 0.8 V; input pulse

falling edge = 50 ns/V;

threshold VCLI = 1.4 V;

see Fig.7

−

115

−

Output clamping and blanking input (HFB; pin 11)

VHFB

output clamping and

blanking input signal

note 9

no blanking, no output

clamping

−0.1

−

+0.8

blanking, no output

clamping

−

2.6

blanking, output clamping

3.5

−

IHFB

input current

VHFB = 0.8 V

−−0.4

−µA

pin 11 connected to ground;

note 8

−80

−45

−30

µA

VHFB = −0.1 V; note 8

−250

−135

−100

µA

tW(HFB)

width of output clamping

pulse

VHFB =3V

−−

µs

Video signal inputs; channels 1, 2 and 3 (pins 6, 8 and 10)

Vi(n)(b-w)

input voltage; black-to-white

value (pins 6, 8 and 10)

−

0.7

1.0

Ii(n)

DC input current

(pins 6, 8 and 10)

no input clamping;

Vi(n) =Vi(n)(clamp);

Tamb = −20 to +70 °C

0.02

0.20

0.35

µA

during input clamping;

Vi(n) =Vi(n)(clamp) ±0.7 V

±350

±420

±500

µA

Signal blanking

ct(blank)

crosstalk suppression from

input to output during

blanking

control bit DISV = 1;

f = 80 MHz

−−

control bit DISV = 1;

f = 120 MHz

−−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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