M65KA512AB datasheet(10/55 Pages) STMICROELECTRONICS

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Signal descriptions

M65KA512AB

10/55

2.7

Write Enable (W)

The Write Enable input, W, controls writing.

2.8

Clock Input (K)

The Clock signal, K, is used to clock the Read and Write cycles. During normal operation,

the Clock Enable pin, KE, is High, VIH. The clock signal K can be suspended to switch the

device to the Self-Refresh, Power-Down or Deep Power-Down mode by driving KE Low, VIL.

2.9

Clock Enable (KE)

The Clock Enable, KE, pin is used to control the synchronizing of the signals with Clock

signal K. If KE is High, VIH, the next Clock rising edge is valid. When KE is Low, VIL, the

signals are no longer clocked and data Read and Write cycles are extended. KE is also

involved in switching the device to the Self-Refresh, Power-Down and Deep Power-Down

modes.

2.10

Lower/Upper Data Input/Output Mask (LDQM, UDQM)

Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals

used to mask the Read or Write data. The DQM latency is two clock cycles for read

operations and there is no latency for write operations.

2.11

VDD Supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (Read and Write).

2.12

VDDQ Supply voltage

VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered

independently of VDD. VDDQ can be tied to VDD or can use a separate supply.

It is recommended to power-up and power-down VDD and VDDQ together to avoid certain

conditions that would result in data corruption.

2.13

VSS Ground

Ground, VSS, is the reference for the core power supply. It must be connected to the system

ground.

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