EVAL-ADN2804EBZ datasheet(21/24 Pages) AD

21 / 24 page

Data Sheet

ADN2804

Rev. D | Page 21 of 24

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance, especially on Pin 23, which is the ground return for

the output buffers. The exposed pad should be connected to the

GND plane using plugged vias so that solder does not leak

through the vias during reflow.

Use of a 22 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they

should be placed between ADN2804 supply pins VCC and VEE,

as close as possible to the ADN2804 VCC pins.

If connections to the supply and ground are made through

vias, the use of multiple vias in parallel helps to reduce series

inductance, especially on Pin 24, which supplies power to the

high speed CLKOUTP/CLKOUTN and DATAOUTP/

DATAOUTN output buffers. Refer to Figure 24 for the

recommended connections.

By placing the power supply and GND planes adjacent to each

other and using close spacing between the planes, excellent high

frequency decoupling can be realized. The capacitance is given

 

0.88ε

PLANE 

where:



is the dielectric constant of the PCB material.

is the area of the overlap of power and GND planes (cm2).

is the separation between planes (mm).

For FR-4, r = 4.4 and d = 0.25 mm; therefore,

CPLANE

~ 15.5A (pF)

µC

I2C CONTROLLER

LOS

SDA

SCK

SADDR5

50Ω TRANSMISSION LINES

DATAOUTP

DATAOUTN

CLKOUTP

CLKOUTN

0.1µF

22µF

1nF

0.1µF

1.6µF

0.1µF

0.47µF ±20%

>300MΩ INSULATION RESISTANCE

1nF

0.1µF

1nF

VCC

50Ω

TIA

RTH

VCC

µC

VCC

TEST1

VCC

VREF

NIN

SLICEP

SLICEN

VEE

VCC

VEE

VCC

VEE

EXPOSED PAD

TIED OFF TO

VEE PLANE

WITH VIAS

Figure 24. Typical ADN2804 Applications Circuit

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