AD7293BCPZ datasheet(14/79 Pages) AD

14 / 79 page

AD7293

Data Sheet

Rev. D | Page 14 of 79

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FACTORY TEST

GPIO4/ALERT1

GPIO5/SLEEP0

GPIO6/SLEEP1

RESET

GPIO7/LDAC

SCLK

DIN

DOUT

DGND

VDRIVE

DVDD

DACVDD-UNI

REFADC

PAVDD

PA_ON

RS0+

RS0–

RS1+

RS1–

AGND

RS2+

RS2–

RS3+

RS3–

VCLAMP0

VCLAMP1

TOP VIEW

(Not to Scale)

AD7293

NOTES

1. EXPOSED PAD. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF THE

PACKAGE. CONNECT THE EXPOSED PAD TO AVSS USING MULTIPLE VIAS OR

LEAVE IT FLOATING.

Figure 7. Pin Configuration

Table 11. Pin Function Descriptions

Pin Number

Mnemonic

Description

FACTORY TEST

Factory Test Pin. Leave this pin unconnected, or connect it to DGND.

GPIO4/ALERT1

General-Purpose Input/Output 4 Pin (GPIO4).

Alert 1 Pin (ALERT1, Default). When configured as an alert, this pin acts as an out of range

indicator. The polarity of the pin is register selectable. This pin is an open-drain output, and

requires a pull-up resistor connected to VDRIVE.

GPIO5/SLEEP0

General-Purpose Input/Output 5 Pin (GPIO5).

Sleep 0 Pin (SLEEP0, Default). DAC power-down digital input pin (polarity is register

selectable). This pin can be configured to trigger DAC clamping on any combination of DAC

channels.

GPIO6/SLEEP1

General-Purpose Input/Output 6 Pin (GPIO6).

Sleep 1 Pin (SLEEP1, Default). DAC power-down digital input pin (polarity is register

selectable). This pin can be configured to trigger DAC clamping on any combination of DAC

channels.

RESET

Reset Input. Taking this pin low performs a hardware reset.

GPIO7/LDAC

General-Purpose Input/Output 7 Pin (GPIO7).

DAC Load Pin (LDAC, Default). When this input is active, the DAC registers are updated. The

polarity of this pin is register selectable. See the Load DAC (LDAC Pin) section for more

information.

SCLK

SPI Serial Clock Input.

Chip Select Signal. This active low, logic input signal frames the serial data input.

DIN

SPI Serial Data Input. The serial data loaded into the registers is provided on this pin. Data is

clocked into the device on the rising edge of SCLK.

DOUT

SPI Serial Data Output. The serial data read from the registers is provided on this pin. Data is

clocked out on the falling edge of SCLK. DOUT is high impedance when it is not outputting

data.

AD7293BCPZ bảng dữ liệu(PDF) 14 Page - Analog Devices

AD7293BCPZ bảng dữ liệu(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

bảng dữ liệu tải về

Link URL