STPMIC25APQR datasheet(24/145 Pages) STMICROELECTRONICS

24 / 145 page

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

1.8 V < VOUT < 3.3 V, HP mode

VOUT-OVR

Power-up overshoot

2.8 V < VBUCKIN < 5.5 V, IOUT = 1 mA, TA = 25 °C

1.5 V < VOUT< 4.2 V

tLP-HP-BCK

Recovery time from

LP to HP mode

VOUT_LP = VOUT_HP

60 (4)

µs

tSU_BCK

Startup delay (delay

before voltage starts

to rise)

Delay time from PWRCTRL signal

(PWRCTRL_DLY =0)

25 (3)

40 (4)

µs

tSS_BCK

Soft-start duration

2.8 V < VBUCKIN<5.5 V

1 mA < IOUT <100 mA

VOUT=4.2 V

235

400

µs

SRBCK

Output voltage slew

rate

Slew rate during startup

10.3

17.5

mV/µs

DVS slew rate of a voltage programmed change low to high or high to

low, from VOUT = 1.5 V to 4.2 V

3.1

tSD_BCK

Shutdown duration

From VOUT = 3.3 V to VOUT < 0.2 V,

2.8 V < VBUCKIN < 5.5 V, IOUT < 1 mA

slow PD

1.5

From VOUT = 3.3 V to VOUT < 0.2 V,

2.8 V < VBUCKIN < 5.5 V, IOUT < 1 mA

fast PD

0.3

1. Guaranteed by design - not tested in production. Load transient performances are strongly impacted by the external passive components

characteristics. The load transient is also influenced by the parasitic elements of the PCB layout. For more info see the forthcoming AN.

2. The output ripple voltage is the result of the inductor ripple current flowing through the output capacitor and depends on the capacitance

value, ESR, and ESL. The actual output ripple voltage is also influenced by the parasitic elements of the PCB layout.

3. See 1: startup sequence.

4. Guaranteed by design - not tested in production.

STPMIC25

Electrical and timing characteristics

DS14278 - Rev 3

page 24/145

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