STPMIC25APQR datasheet(94/145 Pages) STMICROELECTRONICS

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6.5.5

BUCKx PWRCTRL control register (BUCKx_PWRCTRL_CR) (x = 1 to 7)

Table 58. BUCKx_PWRCTRL_CR

PWRCTRL_DLY_H[1:0]

PWRCTRL_DLY_L[1:0]

PWRCTRL_SEL[1:0]

PWRCTRL_RST

PWRCTRL_EN

R/W

•

Address: 0x24/0x29/0x2E/0x33/0x38/0x3D/0x42

•

Default: 0x00

•

Description: BUCK1 to BUCK7 PWRCTRL control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

allocate a PWRCTRL signal for controlling the BUCKx (see Section 5.4.6).

[7:6]

PWRCTRL_DLY_H[1:0]: BUCKx control/reset source shift delay from low to High level

00: no delay

01: 1.5 ms delay

10: 3 ms delay

11: 6 ms delay

[5:4]

PWRCTRL_DLY_L[1:0]: BUCKx control/reset source shift delay from high to Low level

00: no delay

01: 1.5 ms delay

10: 3 ms delay

11: 6 ms delay

[3:2]

PWRCTRL_SEL[1:0]: BUCKx control/reset PWRCTRL source selection

00: No control source

01: PWRCTRL1 control source

10: PWRCTRL2 control source

11: PWRCTRL3 control source

[1]

PWRCTRL_RST: BUCKx independent reset source enable

0: no effect

1: reset enable (when the selected PWRCTRL source is active, BUCKx is disabled and the BUCKx control registers are

reset to the default value. When the selected PWRCTRL source is inactive, BUCKx operates according to

BUCKx_MAIN_CR1 / 2. See Table 27).

[0]

PWRCTRL_EN: BUCKx control source enable

0: disable (BUCKx operates according to BUCKx_MAIN_CR1 / 2)

1: enable (BUCKx operates according to BUCKx_MAIN_CR1 / 2 or BUCKx_ALT_CR1 / 2 depending on the PWRCTRL

selected source. See Table 27).

STPMIC25

DS14278 - Rev 3

page 94/145

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