S3F8S45 datasheet(97/392 Pages) ZILOG

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PS032207-0418

P R E L I M I N A R Y

Interrupt Source Polling Sequence

S3F8S45 MCU

Product Specification

1. Reset (clear to 0) the interrupt enable bit in the SYM Register (SYM.0) to disable all

subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.



When the interrupt service routine is completed, the CPU issues an Interrupt Return

(IRET). This IRET restores the PC and status flags and sets SYM.0 to 1, allowing the CPU

to process the next interrupt request.

5.20. Generating Interrupt Vector Addresses

The interrupt vector area in ROM (00h–FFh) contains the addresses of interrupt service

routines that correspond to each level in the interrupt structure. Vectored interrupt pro-

cessing observes the following sequence:

1. Push the program counter’s low-byte value to the stack.

2. Push the program counter’s high-byte value to the stack.

3. Push the Flags Register values to the stack.

4. Fetch the service routine’s high-byte address from the vector location.

5. Fetch the service routine’s low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

A 16-bit vector address always begins at an even-numbered ROM address within the

range 00h–FFh.

5.21. Nesting of Vectored Interrupts

It is possible to nest a higher-priority interrupt request while a lower-priority request is

being serviced, as shown in the following sequence.

1. Push the current 8-bit Interrupt Mask (IMR) Register value to the stack (PUSH IMR).

2. Load the IMR Register with a new mask value that enables only the higher-priority

interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher-priority interrupt

will be processed if it occurs).

Note:

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