S3F8S45 datasheet(88/392 Pages) ZILOG

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PS032207-0418

P R E L I M I N A R Y

System Mode Register

S3F8S45 MCU

Product Specification

5.11. System Mode Register

The System Mode (SYM) Register, shown in Table 15, is used to globally enable and dis-

able interrupt processing and to control fast interrupt processing.

P3.3 external interrupt

P3.4 external interrupt

P3.5 external interrupt

P3.6 external interrupt

IRQ6

P3CONH

P3CONL

P03INTL

P03PND

EAh, Set1, Bank1

EBh, Set1, Bank1

E9h, Set1, Bank1

E7h, Set1, Bank1

P3.0 external interrupt

P3.1 external interrupt

P3.2 external interrupt

P0.3 external interrupt

IRQ7

P3CONL

P0CONL

P03INTH

P03PND

EBh, Set1, Bank1

D1h, Set1, Bank1

E8h, Set1, Bank1

E7h, Set1, Bank1

Table 15. System Mode Register (SYM; Set1, Bank0)

Bit

76543210

Reset

0––

R/W

–

R/W

Address

DEh

Mode

Note: R = read only; R/W = read/write.

Bit

Description

[7]

Reserved

[6:5]

Reserved

Note:

1. You can select only one interrupt level at a time for fast interrupt processing.

2. Setting SYM.1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.

3. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a 1

to SYM.0).

Table 14. Interrupt Source Control and Data Registers (Continued)

Note: If an interrupt is unmasked (i.e., Enable Interrupt level) in the IMR Register, the pending and enable

bits of the interrupt should be written after a DI instruction is executed

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