ADN4604

Data Sheet

Rev. A | Page 22 of 40

Table 15 displays the TX advanced control registers. The TX advanced control registers consist of two bytes (16 bits) for each of the 16

output channels. The mapping of register address to output channel is shown in the first column. The TX advanced control registers

provides ultimate flexibility of per port output level and preemphasis boost. Table 13 lists a variety of possible output levels and

preemphasis boost settings and the corresponding TX Drive 0 and TX Drive 1 codes.

Table 15. TX Advanced Control Registers

Address: Channel

Default

Register Name

Bit

Bit Name

Description

0x30: Output 0,

0x32: Output 1,

0x34: Output 2,

0x36: Output 3,

0x38: Output 4,

0x3A: Output 5,

0x3C: Output 6,

0x3E: Output 7,

0x40: Output 8,

0x42: Output 9,

0x44: Output 10,

0x46: Output 11,

0x48: Output 12,

0x4A: Output 13,

0x4C: Output 14,

0x4E: Output 15

0xFF

TX Drive 0

control

7

DRV EN1

0: Driver 1 disabled

1: Driver 1 enabled

6:4

DRV LV1[2:0]

Driver 1 current = decimal(DRV LV1[2:0]) + 1

3

DRV EN0

0: Driver 0 disabled

1: Driver 0 enabled

2:0

DRV LV0[2:0]

Driver 0 current = decimal(DRV LV0[2:0]) + 1

0x31: Output 0,

0x33: Output 1,

0x35: Output 2,

0x37: Output 3,

0x39: Output 4,

0x3B: Output 5,

0x3D: Output 6,

0x3F: Output 7,

0x41: Output 8,

0x43: Output 9,

0x45: Output 10,

0x47: Output 11,

0x49: Output 12,

0x4B: Output 13,

0x4D: Output 14,

0x4F: Output 15

0x00

TX Drive 1

control

7

DRV END

0: Driver D disabled

1: Driver D enabled

6:4

DRV LVD[2:0]

Driver D current = decimal(DRV LVD[2:0]) + 1

3

DRV EN2

0: Driver 2 disabled

1: Driver 2 enabled

2:0

DRV LV2[2:0]

Driver 2 current = decimal(DRV LV2[2:0]) + 1