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S71PL129JC0 bảng dữ liệu(PDF) 127 Page - SPANSION

tên linh kiện S71PL129JC0
Giải thích chi tiết về linh kiện  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-bit) CMOS3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory
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October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
125
Advance
Informatio n
64M pSRAM
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
128M pSRAM
Notes:
Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured after 60ms
from the time when standby mode is set up.
Item
Symbol
Test Conditions
Min Typ Max Unit
Average Operating
Current
ICC1
Cycle time=1µs, 100% duty, IIO=0mA,
CS1#
≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2
≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
—
— TBD mA
ICC2
Async
Cycle time=Min, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN=VIH or VIL
—
— TBD mA
Page
Cycle time=tRC+3tPC, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN-VIH or VIL
45
mA
Standby Current (CMOS)
ISB1 (Note 1)
Other inputs=0-VCC
1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1#
controlled) or
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
—
— 120
µA
Item
Symbol
Test Conditions
Min Typ Max Unit
Average Operating
Current
ICC1
Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V,
LB#
≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or
VIN≥VCC-0.2V
—
— TBD mA
ICC2
Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL,
CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL
—
— TBD mA
Standby Current (CMOS) ISB1 (Note 1)
Other inputs=0-VCC
1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
—
— TBD µA



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