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S71PL129JC0 bảng dữ liệu(PDF) 124 Page - SPANSION

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Giải thích chi tiết về linh kiện  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-bit) CMOS3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory
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S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
Advance
Info rmation
Legend:X = Don’t care (must be low or high state).
Absolute Maximum Ratings
Notes:
1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating
conditions longer than one second may affect reliability.
DC Recommended Operating Conditions
Notes:
1. TA=-40 to 85°C, unless otherwise specified.
2. Overshoot: VCC+1.0V in case of pulse width ≤ 20ns.
3. Undershoot: -1.0V in case of pulse width ≤ 20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance
(Ta = 25°C, f = 1 MHz)
Note: This parameter is sampled periodically and is not 100% tested.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to VSS
VIN , VOUT
-0.2 to VCC+0.3V
V
Voltage on VCC supply relative to VSS
VCC
-0.2 to 3.6V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
°C
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Power Supply Voltage
2.7
2.9
3.1
V
VSS
Ground
0
0
0
VIH
Input High Voltage
2.2 (16Mb, 32Mb, 128Mb)
0.8 x VCC (64Mb
—
VCC + 0.3 (16Mb, 32Mb, 128Mb)
VCC + 0.2 (64Mb)
(Note 2)
VIL
Input Low Voltage
-0.2 (Note 3)
—
0.6
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
VIN = 0V
—
8
pF
CIO
Input/Output Capacitance
VOUT = 0V
—
10
pF



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