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S71PL129JC0 bảng dữ liệu(PDF) 69 Page - SPANSION |
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S71PL129JC0 bảng dữ liệu(HTML) 69 Page - SPANSION |
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69 / 153 page ![]() October 28, 2005 S71PL129Jxx_00_A8 S71PL129JC0/S71PL129JB0/S71PL129JA0 67 Advance Informatio n VCC RampRate All DC characteristics are specified for a VCC ramp rate > 1V/100 µs and VCC >=VCCQ - 100 mV. If the VCC ramp rate is < 1V/100 µs, a hardware reset required.+ Read Operations Notes: 1. Not 100% tested. 2. See Figure 9 and Table 16 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE# high to the data bus driven to VCC /2 is taken as tDF. 4. S29PL129J has two CE# (CE1#, CE2#). 5. Valid CE1# / CE2# conditions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) or (CE1# = VIH, CE2# = VIH) 6. Valid CE1# / CE2# transitions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) to (CE1# = CE2# = VIH) 7. Valid CE1# / CE2# transitions: (CE1# = CE2# = VIH) to (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) 8. For 70pF Output Load Capacitance, 2 ns is added to the above tACC,tCE,tPACC,tOE values for all speed grades Figure 10. Input Waveforms and Measurement Levels Table 18. Read-Only Operations Parameter Description Test Setup Speed Options JEDEC Std. 55 60 65 70 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 60 65 70 ns tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 55 60 65 70 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 60 65 70 ns tPACC Page Access Time Max 20 25 25 30 ns tGLQV tOE Output Enable to Output Delay Max 20 25 30 ns tEHQZ tDF Chip Enable to Output High Z (Note 3) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 3) Min 5 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns VIO 0.0 V VIO/2 VIO/2 Output Measurement Level In |
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