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XPSM82816PVCAR bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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XPSM82816PVCAR bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 38 page ![]() 6.4 Thermal Information THERMAL METRIC(1) TPSM8281x UNIT SIE (14 PINS) VCA (13 PINS) JEDEC 51-5 EVM JEDEC 51-7 EVM RθJA Junction-to-ambient thermal resistance 45.3 32.2 72.1 26.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29 n/a (2) 37.2 n/a (2) °C/W RθJB Junction-to-board thermal resistance 27.4 n/a (2) 21.2 n/a (2) °C/W ΨJT Junction-to-top characterization parameter 5.7 7.2 (-0.4)(3) (-1.9)(3) °C/W ΨJB Junction-to-board characterization parameter 16.2 12.7 20.8 10.1 °C/W (1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. (2) Not applicable to an EVM. (3) The junction temperature is lower than the inductor temperature leading to a temperature increase towards the top of the package 6.5 Electrical Characteristics Over operating junction remperature range (TJ = –40°C to +125°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Quiescent current EN = High, no load, device not switching, MODE/SYNC = GND, VOUT = 0.6 V 18 36 μA ISD Shutdown current EN = GND 0.15 90 μA VUVLO Undervoltage lockout threshold VIN rising 2.45 2.6 2.7 V VIN falling 2.1 2.5 2.6 V TJSD Thermal shutdown threshold TJ rising 180 °C Thermal shutdown hysteresis TJ falling 15 °C CONTROL and INTERFACE VIH,EN Input threshold voltage EN rising 1.05 1.1 1.15 V VIL,EN Input threshold voltage EN falling 0.96 1.0 1.05 V IIH,EN Input leakage current into EN EN = VIN or GND 125 nA VIH Input-threshold voltage at MODE/SYNC 1.1 V VIL Input-threshold voltage at MODE/SYNC 0.3 V IIH Input leakage current into MODE/SYNC 250 nA fSW PWM switching frequency range MODE/SYNC = high 1.8 2.25 4 MHz fSW PWM switching frequency COMP/FSET = GND or VIN 2.08 2.25 2.4 MHz fSW PWM switching frequency tolerance using a resistor from COMP/FSET to GND –12% 12% fSYNC Frequency range on MODE/SYNC pin for synchronization 1.8 4 MHz tSync_lock Time to lock to external frequency 50 µs Duty cycle of synchronization signal at MODE/SYNC 20% 80% tDelay Enable delay time Time from EN high to device starts switching; VIN applied already 135 270 520 µs tRamp Output voltage ramp time, SS/TR pin open IOUT = 0 mA, time from device starts switching to power good; device not in current limit 90 150 220 µs ISS/TR SS/TR source current 8 10 12 µA RDIS,SS/T R Internal discharge resistance on SS/TR EN = low 0.7 1.1 1.5 kΩ Tracking gain VFB / VSS/TR 1 www.ti.com TPSM82816 SLUSEY7A – DECEMBER 2022 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM82816 |
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