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TPSM82816PVCAR bảng dữ liệu(PDF) 13 Page - Texas Instruments

tên linh kiện TPSM82816PVCAR
Giải thích chi tiết về linh kiện  TPSM8281x 2.7V to 6V Input 4A / 6A Step-Down Power Module with Integrated Inductor, Frequency Synchronization in MicroSIP™ and MagPack™ Package
PDF  38 Pages
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Trang chủ  http://www.ti.com
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TPSM82816PVCAR bảng dữ liệu(HTML) 13 Page - Texas Instruments

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variation is typically between the nominal switching frequency and up to 288 kHz above the nominal switching
frequency. When the device is externally synchronized, the TPSM8281x follows the external clock and the
internal spread spectrum block is turned off. SSC is also disabled during soft start.
7.3.6 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
MOSFETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the input
voltage goes below the falling threshold.
7.3.7 Power-Good Output (PG)
The device has a power-good output with window comparator. The PG pin goes high impedance after the FB
pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low after the voltage falls
below 90% or rises higher than 110% of the nominal voltage (typical). Table 7-2 shows the typical PG pin logic.
The PG pin is an open-drain output and is specified to sink up to 2 mA. The power good output requires a pullup
resistor connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails
by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.
Table 7-2. Power-Good Pin Logic
DEVICE STATE
PG LOGIC STATUS
HIGH IMPEDANCE
LOW
Enabled (EN = High)
0.95 × VFB_NOM ≤ VFB ≤ 1.07 × VFB_NOM
√
VFB < 0.9 × VFB_NOM or VFB > 1.1 ×
VFB_NOM
√
Shutdown (EN = Low)
√
UVLO
2 V ≤ VIN < VUVLO
√
Thermal Shutdown
TJ > TJSD
√
Power Supply Removal
VIN < 2 V
undefined
The PG pin has a 40-μs deglitch time on the falling edge. See Figure 7-1.
VO
VTH,PG
VTH,PG
PG
UVP
VTH,PG
VTH,PG
OVP
tPG,DLY
tPG,DLY
tPG,DLY
tPG,DLY
Figure 7-1. Power-Good Transient and Delay Behavior
7.3.8 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 180°C
(typical), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and
PG goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal
operation, beginning with soft start. During PFM the thermal shutdown is not active.
www.ti.com
TPSM82816
SLUSEY7A – DECEMBER 2022 – REVISED JUNE 2024
Copyright © 2024 Texas Instruments Incorporated
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