XRT83SL314 datasheet(38/83 Pages) EXAR

38 / 83 page

XRT83SL314

REV. 1.0.1

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

4.0

TRANSMIT PATH LINE INTERFACE

The transmit path of the XRT83SL314 LIU consists of 14 independent T1/E1/J1 transmitters. The following

section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs.

simplified block diagram of the transmit path is shown in Figure 29.

FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH

4.1

TCLK/TPOS/TNEG Digital Inputs

In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has

no function and can be left unconnected. The XRT83SL314 can be programmed to sample the inputs on

either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising

edge of TCLK, set TCLKE to "1" in the appropriate global register. Figure 30 is a timing diagram of the transmit

input data sampled on the falling edge of TCLK. Figure 31 is a timing diagram of the transmit input data

sampled on the rising edge of TCLK. The timing specifications are shown in Table 8.

FIGURE 30. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK

FIGURE 31. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK

HDB3/B8ZS

Encoder

Tx Jitter

Attenuator

Timing

Control

Tx Pulse Shaper

& Pattern Gen

Line Driver

TTIP

TRING

TCLK

TNEG

TPOS

TCLK

TPOS

TNEG

TCLK

TPOS

TNEG

TCLK

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