XRT86VL32IB datasheet(37/65 Pages) EXAR

37 / 65 page

XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

RDY

Ready/Data Transfer Acknowledge Output:

The exact behavior of this pin depends upon the type of Micro-

processor/Microcontroller the XRT86VL32 has been configured

to operate in, as defined by the PTYPE[2:0] pins.

Intel Asynchronous Mode - RDY* - Ready Output

Tis output pin will function as the “active-low” READY output.

During a READ or WRITE cycle, the Microprocessor Interface

block will toggle this output pin to the logic low level, ONLY

when the Microprocessor Interface is ready to complete or ter-

minate the current READ or WRITE cycle. Once the Micropro-

cessor has determined that this input pin has toggled to the

logic “low” level, then it is now safe for it to move on and exe-

cute the next READ or WRITE cycle.

If (during a READ or WRITE cycle) the Microprocessor Inter-

face block is holding this output pin at a logic “high” level, then

the Microprocessor is expected to extend this READ or WRITE

cycle, until it detects this output pin being toggled to the logic

low level.

Motorola Asynchronous Mode - DTACK* - Data Transfer

Acknowledge Output

Tis output pin will function as the “active-low” DTACK output.

During a READ or WRITE cycle, the Microprocessor Interface

block will toggle this output pin to the logic low level, ONLY

when the Microprocessor Interface is ready to complete or ter-

minate the current READ or WRITE cycle. Once the Micropro-

cessor has determined that this input pin has toggled to the

logic “low” level, then it is now safe for it to move on and exe-

cute the next READ or WRITE cycle.

If (during a READ or WRITE cycle) the Microprocessor Inter-

face block is holding this output pin at a logic “high” level, then

the Microprocessor is expected to extend this READ or WRITE

cycle, until it detects this output pin being toggled to the logic

low level.

Power PC 403 Mode - RDY Ready Output:

This output pin will function as the “active-high” READY output.

During a READ or WRITE cycle, the Microprocessor Interface

block will toggle this output pin to the logic high level, ONLY

when the Microprocessor Interface is ready to complete or ter-

minate the current READ or WRITE cycle. Once the Micropro-

cessor has sampled this signal being at the logic “high” level

upon the rising edge of PCLK, then it is now safe for it to move

on and execute the next READ or WRITE cycle.

If (during a READ or WRITE cycle) the Microprocessor Inter-

face block is holding this output pin at a logic “low” level, then

the Microprocessor is expected to extend this READ or WRITE

cycle, until it samples this output pin being at the logic low

level.

NOTE:

The Microprocessor Interface will update the state of

this output pin upon the rising edge of PCLK.

MICROPROCESSOR INTERFACE

SIGNAL NAME

BALL #TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

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