XRT79L71IB datasheet(69/434 Pages) EXAR

69 / 434 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - REGISTER/MAP DESCRIPTION

6 - 4

Chunk_Size[2:0]/

TxFIFOPacket Fill

Level[2:0]

Continued

R/W

If the Transmit POS-PHY Interface block is operating in the

Packet Mode

If the user has configured the Transmit POS-PHY Interface block

to operate in the Packet Mode, then these three bit-fields permit

the user to specify the minimum amount of empty space that

must exist (within the TxFIFO) before the Transmit POS-PHY

Interface block will drive the TxPPA output pin "High" when

polled. The following table presents the relationship between the

contents of these three bit-fields and the corresponding amount

of empty space (in terms of bytes) that must exist within the

TxFIFO in order to assert the TxPPA output pin.

3 -2

Transmit POS-PHY Data

Bus Width[1:0]

R/W

Transmit POS-PHY Data Bus Width[1:0]:

These two READ/WRITE bit-fields permit the user to select/

specify the width of the Transmit POS-PHY Data Bus. The fol-

lowing table presents the relationship between the contents

within these two bit-fields and the corresponding width of the

Transmit POS-PHY Data Bus.

BIT NUMBER

NAME

TYPE

DESCRIPTION

TxFIFO Packet

Fill Level[2:0]

000

001

010

011

100

101

11X

Amount of Empty Space Required

(within the TxFIFO) to Assert

TxPPA

4 Bytes

8 Bytes

16 Bytes

32 Bytes

64 Bytes

128 Bytes

Do Not Use

Transmit POS-PHY

Data Bus Width[1:0]

Width of Transmit

POS-PHY Data Bus

Inactive

Unused

16 - bits

8 - bits

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