MPC866PCZP100A datasheet(46/96 Pages) FREESCALE

46 / 96 page

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

IEEE 1149.1 Electrical Specifications

Figure 36 shows the reset timing for the debug port configuration.

Figure 36. Reset Timing—Debug Port Configuration

11 IEEE 1149.1 Electrical Specifications

Table 15 shows the JTAG timings for the MPC866/859 shown in Figure 37 through Figure 40.

Table 15. JTAG Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

J82

TCK cycle time

100.00

—

J83

TCK clock pulse width measured at 1.5 V

40.00

—

J84

TCK rise and fall times

0.00

10.00

J85

TMS, TDI data setup time

5.00

—

J86

TMS, TDI data hold time

25.00

—

J87

TCK low to TDO data valid

—

27.00

J88

TCK low to TDO data invalid

0.00

—

J89

TCK low to TDO high impedance

—

20.00

J90

TRST assert time

100.00

—

J91

TRST setup time to TCK low

40.00

—

J92

TCK falling edge to output valid

—

50.00

J93

TCK falling edge to output valid out of high impedance

—

50.00

J94

TCK falling edge to output high impedance

—

50.00

J95

Boundary scan input valid to TCK rising edge

50.00

—

J96

TCK rising edge to boundary scan input invalid

50.00

—

CLKOUT

SRESET

DSCK, DSDI

R70

R82

R80

R81

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