MPC862_06 datasheet(15/88 Pages) FREESCALE

15 / 88 page

MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Layout Practices

7.6

References

Semiconductor Equipment and Materials International

(415) 964-5111

805 East Middlefield Rd.

Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) Specifications

800-854-7179 or

(Available from Global Engineering Documents)

303-397-7956

JEDEC Specifications

http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive

Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and

Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

Layout Practices

Each VCC pin on the MPC862/857T/857DSL should be provided with a low-impedance path to the board’s

supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power

supply pins drive distinct groups of logic on chip. The V

CC power supply should be bypassed to ground

using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package.

The capacitor leads and associated printed circuit traces connecting to chip V

CC and GND should be kept

to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner

layers as VCC and GND planes.

All output pins on the MPC862/857T/857DSL have fast rise and fall times. Printed circuit (PC) trace

interconnection length should be minimized in order to minimize undershoot and reflections caused by

these fast output switching times. This recommendation particularly applies to the address and data busses.

Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all

device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and

bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the V

CC and GND circuits. Pull up all unused inputs or signals that will be

inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.

Bus Signal Timing

The maximum bus speed supported by the MPC862/857T/857DSL is 66 MHz. Higher-speed parts must

be operated in half-speed bus mode (for example, an MPC862/857T/857DSL used at 80MHz must be

configured for a 40 MHz bus). Table 6 shows the period ranges for standard part frequencies.

Table 6. Period Range for Standard Part Frequencies

Freq

50 MHz

66 MHz

80 MHz

100 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Period

20.00

30.30

15.15

30.30

25.00

30.30

20.00

30.30

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