33989 datasheet(41/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

TYPICAL APPLICATIONS

SUPPLEMENTAL APPLICATION NOTES

Failure on VDD1, Watchdog, Reset, INT Pins

The paragraphs below describe the behavior of the device

and of the INT, RST, and WD pins at power up and under

failure of VDD1.

Power Up and SBC Entering Normal Operation

After a power-up the SBC enters in Normal request mode

(CAN interface is in TX/RX mode): VDD1 is on, V2 is off. After

350 ms if no watchdog is written (no TIM1 register write) a

reset occurs, and the SBC returns to normal request

mode.During this sequence WD is active (low level).

Once watchdog is written the SBC goes to normal mode:

VDD1 is still on and V2 turns on, WD is no longer active and

the reset pin is high. If the watchdog is not refreshed, the SBC

generates a reset and returns to Normal request mode.

Figure 23. Power Up and SBC Entering Normal Operation

Power Up and VDD1 Going Low with Stop Mode as

Default Low Power Mode Selected

The first part of the following figure is identical to the

above. If VDD1 is pulled below the VDD1 under voltage reset

(typ 4.6 V) for instance by an overcurrent or short circuit (ex

short to 4 V), and if a low power mode previously selected

was stop mode, the SBC enters reset mode (reset pin is

active). The pin WD stays high, but the high level (VOH)

follows the VDD1 level. The interrupt pin goes low.

When the VDD1 overload condition is removed, the SBC

restarts in Normal request mode.

Figure 24. Power Up and VDD1 Going Low with Stop Mode as Default Low Power Mode Selected

VDD1

SPI (CS)

INT

RST

SBC in

RESET

mode

SBC in Normal request

mode

SBC in Normal

mode

SBC in Normal

request mode

SBC in Normal

mode

350 ms

Reset every 350 ms

Write Watchdog each X ms

No Watchdog is written

SBC in Normal request

mode

SBC in Normal

mode

SBC in Reset

mode

SBC in Normal

Request mode

350 ms

SBC in

RESET

mode

350 ms

VDD1

SPI (CS)

INT

RST

Reset every 350 ms

No problem on

Watchdog period

Write Watchdog

each X ms

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