56F8366 datasheet(136/184 Pages) FREESCALE

136 / 184 page

56F8366 Technical Data, Rev. 6

136

Freescale Semiconductor

Preliminary

Figure 7-1 JTAG to FM Connection for Lockout Recovery

Two examples of FM_CLKDIV calculations follow.

EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up,

the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation

yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This

translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.

EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM

input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] = 1. Using the

following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of

181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.

Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock

divider value must be shifted into the corresponding 7-bit data register. After the data register has been

updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout

sequence to commence. The controller must remain in this state until the erase sequence has completed.

For details, see the JTAG Section in the 56F8300 Peripheral User Manual.

Note:

Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller

(by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured

operation.

SYS_CLK

JTAG

FMCLKD

DIVIDER

FM_CLKDIV

FM_ERASE

Flash Memory

clock

input

SYS_CLK

(2)

)

(

(DIV + 1)

150[kHz]

200[kHz]

)

(

(DIV + 1)

150[kHz]

200[kHz]

SYS_CLK

(2)(8)

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