56F8366 datasheet(114/184 Pages) FREESCALE

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56F8366 Technical Data, Rev. 6

114

Freescale Semiconductor

Preliminary

5.7 Resets

5.7.1

Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset

vector will be presented until the second rising clock edge after RESET is released.

5.7.2

ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,

except the core IRQs with fixed priorities:

•

Illegal Instruction

•

SW Interrupt 3

•

HW Stack Overflow

•

Misaligned Long Word Access

•

SW Interrupt 2

•

SW Interrupt 1

•

SW Interrupt 0

•

SW Interrupt LP

These interrupts are enabled at their fixed priority levels.

Part 6 System Integration Module (SIM)

6.1 Overview

The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls

distribution of resets and clocks and provides a number of control features. The system integration module

is responsible for the following functions:

•

Reset sequencing

•

Clock generation & distribution

•

Stop/Wait control

•

Pull-up enables for selected peripherals

•

System status registers

•

Registers for software access to the JTAG ID of the chip

•

Enforcing Flash security

There are discussed in more detail in the sections that follow.

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