56F8335 datasheet(55/160 Pages) FREESCALE

55 / 160 page

Peripheral Memory Mapped Registers

56F8335 Technical Data, Rev. 5

Freescale Semiconductor

Preliminary

Table 4-18 Quadrature Decoder 1 Registers Address Map

(DEC1_BASE = $00 F190)

Quadrature Decoder 1 is NOT available in the 56F8135 device

Address Offset

DEC1_DECCR

Decoder Control Register

DEC1_FIR

Filter Interval Register

DEC1_WTR

Watchdog Time-out Register

DEC1_POSD

Position Difference Counter Register

DEC1_POSDH

Position Difference Counter Hold Register

DEC1_REV

Revolution Counter Register

DEC1_REVH

Revolution Hold Register

DEC1_UPOS

Upper Position Counter Register

DEC1_LPOS

Lower Position Counter Register

DEC1_UPOSH

Upper Position Hold Register

DEC1_LPOSH

Lower Position Hold Register

DEC1_UIR

Upper Initialization Register

DEC1_LIR

Lower Initialization Register

DEC1_IMR

Input Monitor Register

Table 4-19 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0)

Address Offset

IPR 0

Interrupt Priority Register 0

IPR 1

Interrupt Priority Register 1

IPR 2

Interrupt Priority Register 2

IPR 3

Interrupt Priority Register 3

IPR 4

Interrupt Priority Register 4

IPR 5

Interrupt Priority Register 5

IPR 6

Interrupt Priority Register 6

IPR 7

Interrupt Priority Register 7

IPR 8

Interrupt Priority Register 8

IPR 9

Interrupt Priority Register 9

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