56F8335 datasheet(44/160 Pages) FREESCALE

44 / 160 page

56F8335 Technical Data, Rev. 5

Freescale Semiconductor

Preliminary

4.7 Peripheral Memory Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may

be accessed with the same addressing modes used for ordinary Data memory, except all peripheral

registers should be read/written using word accesses only.

Table 4-9 summarizes base addresses for the set of peripherals on the 56F8335 and 56F8135 devices.

Peripherals are listed in order of the base address.

The following tables list all of the peripheral registers required to control or access the peripherals.

Note: Features in italics are NOT available in the 56F8135 device.

X:$FF FFFE

OTX / ORX (32 bits)

Transmit Register / Receive Register

X:$FF FFFF

OTX1 / ORX1

Transmit Register Upper Word

Receive Register Upper Word

Table 4-9 Data Memory Peripheral Base Address Map Summary

Peripheral

Prefix

Base Address

Table Number

External Memory Interface

EMI

X:$00 F020

4-10

Timer A

TMRA

X:$00 F040

4-11

Timer B

TMRB

X:$00 F080

4-12

Timer C

TMRC

X:$00 F0C0

4-13

Timer D

TMRD

X:$00 F100

4-14

PWM A

PWMA

X:$00 F140

4-15

PWM B

PWMB

X:$00 F160

4-16

Quadrature Decoder 0

DEC0

X:$00 F180

4-17

Quadrature Decoder 1

DEC1

X:$00 F190

4-18

ITCN

X:$00 F1A0

4-19

ADC A

ADCA

X:$00 F200

4-20

ADC B

ADCB

X:$00 F240

4-21

Temperature Sensor

TSENSOR

X:$00 F270

4-22

SCI #0

SCI0

X:$00 F280

4-23

SCI #1

SCI1

X:$00 F290

4-24

SPI #0

SPI0

X:$00 F2A0

4-25

SPI #1

SPI1

X:$00 F2B0

4-26

COP

X:$00 F2C0

4-27

PLL, OSC

CLKGEN

X:$00 F2D0

4-28

GPIO Port A

GPIOA

X:$00 F2E0

4-29

GPIO Port B

GPIOB

X:$00 F300

4-30

Table 4-8 EOnCE Memory Map (Continued)

Address

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