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IA88C00-PDW48I-R bảng dữ liệu(PDF) 38 Page - InnovASIC, Inc

tên linh kiện IA88C00-PDW48I-R
Giải thích chi tiết về linh kiện  Microcontroller
PDF  80 Pages
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nhà sản xuất  INNOVASIC [InnovASIC, Inc]
Trang chủ  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

IA88C00-PDW48I-R bảng dữ liệu(HTML) 38 Page - InnovASIC, Inc

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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright © 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 38 of 80
1.888.824.4184
D0 - Handshake Enable - When this bit is set to 1, the handshake function is enabled.
D1 - Port Select - This bit selects which port is controlled by Handshake Channel 0. When it is set to 1,
Port 1 is selected and when it is cleared to 0, Port 4 is selected.
D2 - DMA Enable - When this bit is set to 1, the DMA function is enabled for Handshake Channel 0.
When it is cleared to 0, the DMA function is not used by the handshake channel and may be used by the
UART.
D3 - Mode - When this bit is set to 1, the "fully interlocked" mode is enabled. When it is cleared to 0, the
"strobed" mode is enabled.
D4-D7 - Deskew Counter - This 4-bit field is used to select a count value from 1 to 16 (0000-1111). This
value is the number of processor clocks used to generate the set-up and strobe when using the "strobed"
mode, or the set-up when using the "fully-interlocked" mode.
Figure 37. Handshake 1 Control (H1C), R245 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
X
X
X
X
X
X
X
0
Read/Write
W/O
W/O
W/O
W/O
W/O
W/O
W/O
W/O
This register controls Handshake Channel 1.
D0 - Handshake Enable - When this bit is set to 1, the handshake function is enabled.
D1 - Not Used.
D2 - Not Used.
D3 - Mode - When this bit is set to 1, the "fully interlocked" mode is enabled. When it is cleared to 0, the
"strobed" mode is enabled.
D4-D7 - Deskew Counter - This 4-bit field is used to select a count value from 1 to 16 (0000-1111). This
value is the number of processor clocks used to generate the set-up and strobe when using the "strobed"
mode, or the set-up when using the "fully-interlocked" mode.
Figure 38. Port 4 Direction Control Register (P4D), R246 Bank 0
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial Value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W



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