PAC7112 datasheet(29/56 Pages) FREESCALE

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ElectricalCharacteristics

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Freescale Semiconductor

3.11 Serial Peripheral Interface

3.11.1 Master Mode

Master mode timing values are shown in Table 32 and illustrated in Figure 11 and Figure 12.

3.11.2 Slave Mode

Slave mode timing values are shown in Table 33 and illustrated in Figure 13 and Figure 14.

Table 32. SPI Master Mode Timing Characteristics

Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

U1a

P Operating Frequency (baud rate)

fOP

NOTES:

1. Refer to MAC7100 Microcontroller Family Reference Manual (MAC7100RM) Chapter 22 for all available baud rates.

—½ 2

2. On mask set L49P and L47W devices, U1a maximum = ¼ and U1b minimum = 4.

fIPS

U1b

P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)tSCK

2 2

—7

× 32,768

tIPS

D Enable Lead Time

tlead

½—

—

tSCK

D Enable Lag Time

tlag

½—

—

tSCK

D Clock (SCK) High or Low Time

twsck

tIPS − 30

—

1024 tIPS

D Data Setup Time (Inputs)

tsu

—

D Data Hold Time (Inputs)

thi

0—

—

D Data Valid (after Enable Edge)

——

U10

D Data Hold Time (Outputs)

tho

0—

—

U11

D Rise Time Inputs and Outputs

——

U12

D Fall Time Inputs and Outputs

——

Table 33. SPI Slave Mode Timing Characteristics

Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

V1a

P Operating Frequency

fOP

—½ 1

NOTES:

1. On mask set L49P and L47W devices, V1a maximum = ¼ and V1b minimum = 4.

fIPS

V1b

P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)tSCK

2 1

—7

× 32,768

tIPS

D Enable Lead Time

tlead

1—

—

tIPS

D Enable Lag Time

tlag

1—

—

tIPS

D Clock (SCK) High or Low Time

twsck

tIPS − 30

—

D Data Setup Time (Inputs)

tsu

—

D Data Hold Time (Inputs)

thi

—

D Slave Access Time

——

tIPS

D Slave SIN Disable Time

tdis

——

tIPS

D Data Valid (after SCK Edge)

——

V10

D Data Hold Time (Outputs)

tho

0—

—

V11

D Rise Time Inputs and Outputs

——

V12

D Fall Time Inputs and Outputs

——

732 678

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732 678

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