DSP56362P datasheet(113/152 Pages) FREESCALE

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Host Port Considerations

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

5-5

5.4.3

Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF

(MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5%

and approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%.

5.4.4

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL

is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency

of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be

2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the

prescribed values.

5.5

Host Port Considerations

Careful synchronization is required when reading multi-bit registers that are written by another

asynchronous system. This synchronization is a common problem when two asynchronous systems are

connected, as they are in the host interface. The following paragraphs present considerations for proper

operation.

5.5.1

Host Programming Considerations

•

Unsynchronized Reading of Receive Byte Registers

—When reading the receive byte registers,

receive register high (RXH), receive register middle (RXM), or receive register low (RXL), the

host interface programmer should use interrupts or poll the receive register data full (RXDF) flag

that indicates whether data is available. This ensures that the data in the receive byte registers will

be valid.

•

Overwriting Transmit Byte Registers

—The host interface programmer should not write to the

transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit

transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid

data to the host receive (HRX) register.

•

Synchronization of Status Bits from DSP to Host

—HC, HOREQ, DMA, HF3, HF2, TRDY,

TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor

(refer to the user’s manual for descriptions of these status bits). The host can read these status bits

very quickly without regard to the clock rate used by the DSP, but the state of the bit could be

changing during the read operation. This is not generally a system problem, because the bit will be read

correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with

a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be

stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP

changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits

during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has

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