IA82527-PTQ44A-R datasheet(16/45 Pages) INNOVASIC

16 / 45 page

IA82527

04 May 2007

CAN Serial Communications Controller

As of Production Ver. 00

PRELIMINARY



 2007

EN21070504-00

www.Innovasic.com

Customer Support:

Page 16 of 45

1-888-824-4184

Table 3. IA82527 Pin/Signal Descriptions, continued

Signal

Name

PLCC

QFP

Description

ste

a3/ad3/ste

synchronization transmission enable. Input. Serial interface Mode.

The logic level at the ste pin enables the transmission of the

synchronization bytes through the IA82527 miso pin while the master

device transmits the Address and Control Byte as follows:

•

When a logic 0 is placed on the ste pin, the synchronization

bytes sent through the miso pin are 00H and 00H.

•

When a logic 1 is placed on the ste pin, the synchronization

bytes sent through the miso pin are AAH and 55H.

The IA82527 sends the synchronization bytes after the cs_n signal

has been asserted (low).

tx0

—

tx1

—

Transmit (tx), lines 0 and 1. Output (push-pull).

Pins tx0 and tx1 are the outputs from the IA82527 to the Controller

Area Network (CAN) bus lines.

During a recessive bit, tx0 is high and tx1 is low. During a dominant

bit, tx0 is low and tx1 is high.

VCC

—

Power (VCC).

This pin provides power for the IA82527 device. It must be

connected to a +5V DC power source.

VCC/2

int_n/ VCC/2

Reference Voltage, ISO Physical Layer (VCC/2). Output.

The VCC/2 pin provides a reference voltage for the ISO low-speed

physical layer:

•

38V DC (minimum) to 2.60V DC (maximum)

(VCC = +5.00V; IOUT ≤ 75 µA)

This pin only functions as VCC/2 when the MUX bit of the CPU

Interface Register (02H) is 1.

VSS1

—

Ground, Digital (VSS1).

This pin provides the digital ground (0V) for the IA82527. It must be

connected to a VSS board plane.

VSS2

—

Ground, Analog (VSS2).

This pin provides the ground (0V) for the IA82527 analog comparator.

It must be connected to a VSS board plane.

continued

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