TMS320VC5402 datasheet(39/68 Pages) TI

39 / 68 page

TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing

timing requirements for a

memory read (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 13)

MIN

MAX

UNIT

ta(A)M

Access time, read data access from address valid

2H–7

ta(MSTRBL)

Access time, read data access from MSTRB low

2H–8

tsu(D)R

Setup time, read data before CLKOUT low

th(D)R

Hold time, read data after CLKOUT low

–2

th(A-D)R

Hold time, read data after address invalid

th(D)MSTRBH Hold time, read data after MSTRB high

† Address, PS, and DS timings are all included in timings referenced as address.

switching characteristics over recommended operating conditions for a

memory read

(MSTRB = 0)† (see Figure 13)

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid‡

–2

td(CLKH-A)

Delay time, CLKOUT high (transition) to address valid§

–2

td(CLKL-MSL)

Delay time, CLKOUT low to MSTRB low

–1

td(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high

–1

th(CLKL-A)R

Hold time, address valid after CLKOUT low‡

–2

th(CLKH-A)R

Hold time, address valid after CLKOUT high§

–2

† Address, PS, and DS timings are all included in timings referenced as address.

‡ In the case of a memory read preceded by a memory read

§ In the case of a memory read preceded by a memory write

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