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AD9516-3/PCBZ bảng dữ liệu(PDF) 13 Page - Analog Devices |
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AD9516-3/PCBZ bảng dữ liệu(HTML) 13 Page - Analog Devices |
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13 / 84 page ![]() AD9516-3 Rev. 0 | Page 13 of 84 Parameter Min Typ Max Unit Test Conditions/Comments TIMING Clock Rate (SCLK, 1/tSCLK) 25 MHz Pulse Width High, tHI 16 ns Pulse Width Low, tLO 16 ns SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 8 ns CS to SCLK Setup and Hold, tS, tH 2 ns CS Minimum Pulse Width High, tPWH 3 ns PD, SYNC, AND RESET PINS Table 15. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNC TIMING Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK input signal LD, STATUS, REFMON PINS Table 16. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 53, 0x17, 0x1A, and 0x1B Output Voltage High (VOH) 2.7 V Output Voltage Low (VOL) 0.4 V MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling ANALOG LOCK DETECT Capacitance 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range 1.02 MHz Frequency above which the monitor indicates the presence of the reference Extended Range 8 kHz Frequency above which the monitor indicates the presence of the reference LD PIN COMPARATOR Trip Point 1.6 V Hysteresis 260 mV |
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