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AD9516-3/PCBZ bảng dữ liệu(PDF) 29 Page - Analog Devices |
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AD9516-3/PCBZ bảng dữ liệu(HTML) 29 Page - Analog Devices |
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29 / 84 page  AD9516-3 Rev. 0 | Page 29 of 84 Internal VCO and Clock Distribution When using the internal VCO and PLL, the VCO divider must be employed to ensure that the frequency presented to the channel dividers does not exceed its specified maximum frequency (1600 MHz, see Table 3). The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability. When using the internal VCO, it is necessary to calibrate the VCO (0x18<0>) to ensure optimal performance. For internal VCO and clock distribution applications, the register settings shown in Table 24 should be used. Table 24. Settings When Using Internal VCO Register Function 0x10<1:0> = 00b PLL normal operation (PLL on). 0x10 to 0x1E PLL settings. Select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration. 0x18<0> = 0, 0x232<0> = 1 Reset VCO calibration (first time after power-up, this does not have to be done, but must be done subsequently). 0x18<0> = 1, 0x232<0> = 1 Initiate VCO calibration. 0x1E0<2:0> VCO divider set to divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6. 0x1E1<0> = 0b Use the VCO divider as source for distribution section. 0x1E1<1> = 1b VCO selected as the source. |
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