MPC8313CVRAFF datasheet(15/88 Pages) FREESCALE

tên linh kiện	MPC8313CVRAFF

Giải thích chi tiết về linh kiện	PowerQUICC??II Pro Processor Hardware Specifications

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

RESET Initialization

Table 10 provides the PLL lock times.

Time for the device to turn off POR configuration signals with

respect to the assertion of HRESET

—4

Time for the device to turn on POR configuration signals with

respect to the negation of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary

clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.

2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.

3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 10. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs

Table 9. RESET Initialization Timing Specifications (continued)

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