TCS3471 datasheet(24/39 Pages) OSRAM

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[v1-01] 2018-Mar-27

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TCS3471 − Register Description

Persistence Register (0x0C)

The persistence register controls the filtering interrupt

capabilities of the device. Configurable filtering is provided to

allow interrupts to be generated after each integration cycle or

if the integration has produced a result that is outside of the

values specified by the threshold register for some specified

amount of time.

Figure 28:

Persistence Register

Reserved

APERS

Field

Bits

Description

Reserved

7:4

Reserved.

APERS

3:0

Interrupt persistence. Controls rate of interrupt to the host processor.

FIELD VALUE

MEANING

INTERRUPT PERSISTENCE FUNCTION

0000

Every

Every RGBC cycle generates an interrupt

0001

1 clear channel value outside of threshold range

0010

2 clear channel consecutive values out of range

0011

3 clear channel consecutive values out of range

0100

5 clear channel consecutive values out of range

0101

10 clear channel consecutive values out of range

0110

15 clear channel consecutive values out of range

0111

20 clear channel consecutive values out of range

1000

25 clear channel consecutive values out of range

1001

30 clear channel consecutive values out of range

1010

35 clear channel consecutive values out of range

1011

40 clear channel consecutive values out of range

1100

45 clear channel consecutive values out of range

1101

50 clear channel consecutive values out of range

1110

55 clear channel consecutive values out of range

1111

60 clear channel consecutive values out of range

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