| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
SFH5721 bảng dữ liệu(PDF) 27 Page - OSRAM GmbH |
|
|
|||||||||||||||||||||||||||||
SFH5721 bảng dữ liệu(HTML) 27 Page - OSRAM GmbH |
|
27 / 54 page ![]() SFH 5721 DATASHEET DATASHEET 27 | Version 1.1 | 2022-02-28 Interrupt Configuration Register (ICONF) 0x03 Bit NAME R/W Default Description 7:6 - R/W 00 Not used 5 ICC R/W 0 Interrupt Clear Configuration 4 IOA R/W 0 Interrupt Or-And Configuration 3:0 IPERS[3:0] R/W 0000 Persistence Configuration The ICONF register is used to configure the interrupt function of the IC. The register controls the filtering interrupt capability of the device by IPERS[3:0] bits. Configurable filtering is provided to allow interrupts to be generated after each ADC integration cycle or if the ADC integration has produced a result that is outside of the values specified by high or low threshold register for some specified amount of time. When multiple readout channels are enabled, IOA (Interrupt-Or-And) bit determine if interrupt is generated when a single channel generates the interrupt (Or) or if all enabled channels whose interrupt is enabled generate the interrupt (And). Clearing of the interrupt is configured by ICC bit. If one of the Single Shot Modes is activated, the interrupt is activated for 24μs only and then released again. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |