SLRC61002HNSLASHT datasheet(80/139 Pages) NXP

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NXP Semiconductors

SLRC610

High-performance ICODE frontend SLRC610 and SLRC610 plus

9.12.2 RxCtrl

Bit

Symbol

RxAllowBits

RxMultiple

RFU

EMD_Sup

Baudrate

Access

rights

r/w

Table 150. RxCtrl register (address 35h)

Bit

Symbol

Description

RxAllowBits

If set, data is written into FIFO even if CRC is enabled, and no complete byte has been

received.

RxMultiple

If set, RxMultiple is activated and the receiver will not terminate automatically (refer

Section 7.10.3.4 "Receive command").

If set to logic 1, at the end of a received data stream an error byte is

added to the FIFO. The error byte is a copy of the Error register.

5 to 4

RFU

EMD_Sup

Enables the EMD suppression according ISO/IEC14443. If an error occurs within the

first three bytes, these three bytes are assumed to be EMD, ignored and the FIFO

is reset. A collision is treated as an error as well If a valid SOF was received, the

EMD_Sup is set and a frame of less than 3 bytes had been received. RX_IRQ is not set

in this EMD error cases. If RxForceCRCWrite is set, the FIFO should not be read out

before three bytes are written into.

2 to 0

Baudrate

Defines the baud rate of the receiving signal.

2h: 26 kBd

3h: 52 kBd

all remaining values are RFU

Table 151. RxCtrl bits

9.12.3 RxWait

Selects internal receiver settings.

Bit

Symbol

RxWaitEtu

RxWait

Access

rights

r/w

Table 152. RxWait register (address 36h)

Bit

Symbol

Description

RXWaitEtu

If set to 0, the RxWait time is RxWait × 16/13.56 MHz.

If set to 1, the RxWait time is RxWait × (0.5/DBFreq).

6 to 0

RxWait

Defines the time after sending, where every input is ignored.

Table 153. RxWait bits

SLRC610

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Product data sheet

Rev. 5.1 — 3 January 2024

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